@incollection{,
	
					
					
					F7848B4C30E5815BB66B796A17DB836D
				,
	author={{PrachiAgarwal} and {Dr. Anil KumarSharma} and {AdeshKumar} and {}},
	journal={{Global Journal of Computer Science and Technology}},
	journal={{GJCST}}0975-41720975-435010.34257/gjcst,
	address={Cambridge, United States},
	publisher={Global Journals Organisation}131218
}

@incollection{b0,
	
	
		,
	title={{Modeling and Simulation of 2D Mesh Topological Network on Chip (NOC)}}
		,
	author={{
			PrachiAgarwal
		} and {
			AnilKumarSharma
		} and {
			AdeshKumar
		}}
		
		
	
	
		,
	journal={{International Journal of Computer Applications}}
		
			72
			21
			
			,
	year={June 2013}
		
	

}

@incollection{b1,
	
	
		,
	title={{Express Cube Topologies for On-Chip Interconnects}}
		,
	author={{
			BGrot
		} and {
			JHestness
		} and {
			SWKeckler
		} and {
			OMutlu
		}}
		
		
		
	
	
		,
	booktitle={{15th International Symposium on Computer Architecture (HPCA)}}
				
			,
	year={2009}
		
	

}

@incollection{b2,
	
	
		,
	title={{Network-on-Chip design and synthesis outlook}}
		,
	author={{
			DavidAtienzaa
		} and {
			FedericoAngiolini
		} and {
			SrinivasanMurali
		} and {
			AntonioPullinid
		} and {
			LucaBenini
		} and {
			GiovanniDeMicheli
		}}
		
		
		
		
		
	
	
		,
	journal={{INTEGRATION, the VLSI journal Elsevier}}
		
			41
			
			,
	year={2008}
		
	

}

@incollection{b3,
	
	
		,
	title={{A Network-on-Chip Architecture for Gigascale Systems-on-Chip, IEEE Circuits and systems magazine, second quarter}}
		,
	author={{
			DavideBertozzi
		} and {
			LucaBenini
		}}
		
	
	
		,
	journal={{Xpipes}}
		
			
			,
	year={2004}
		
	

}

@incollection{b4,
	
	
		,
	title={{An interconnect architecture for networking systems on chips}}
		,
	author={{
			F
		} and {
			KarimANguyen
		} and {
			SDey
		}}
		
		
	
	
		,
	journal={{IEEE Journal on Micro High Performance Interconnect}}
		
			22
			5
			
			,
	year={Sept 2002}
		
	

}

@book{b5,
	
	
		,
	title={{}}
		,
	author={{
			JasonCong
		} and {
			YuhuiHuang
		} and {
			BoYuan
		}}
		
		
		
			
			,
	address={Los Angeles Los Angeles, USA}
		
		
			Computer Science Department University of California
		
	

}

@book{b6,
	
	
		26.00
		,
	title={{©2011 IEEE, A Tree-Based Topology Synthesis for On-Chip Network}}
				
			
		
	

}

@incollection{b7,
	
	
		,
	title={{Research challenges for on-chip inter connection networks}}
		,
	author={{
			JDOwens
		} and {
			WJDally
		}}
		
	
	
		,
	journal={{IEEE MICRO}}
		
			27
			5
			
			,
	year={Oct. 2007}
		
	

}

@incollection{b8,
	
	
		,
	title={{On-chip communication architecture exploration: A quantitative evaluation of point-topoint, bus, and network-on-chip approaches}}
		,
	author={{
			HGLee
		} and {
			NChang
		} and {
			UYOgras
		} and {
			RMarculescu
		}}
		
		
		
	
	
		,
	journal={{ACM Trans. Des. Autom. Electron. Syst}}
		
			12
			3
			
			,
	year={Aug. 2007}
		
	

}

@book{b9,
	
	
		,
	author={{
			Mohammad Ayoub Khan
		}}
		,
	title={{Abdul Quaiyum Ansari, A Quadrant-XYZ Routing Algorithm for}}
				
			3
		
	

}

@incollection{b10,
	
	
		,
	title={{}}
	
	
		,
	journal={{The Research Bulletin of Jordan ACM}}
		2078-7952
		
			II
			
		
		
			Asymmetric Torus Network-on-Chip
		
	
	,
	note={II) pp}

}

@incollection{b11,
	
	
		,
	title={{White paper on OCCN: A Network-On-Chip Modeling and Simulation Framework, ISD Integrated system developments, page 8. 11. Naveen Chaudhary, Bursty Communication Performance Analysis of Network-on-Chip with Diverse Traffic Permutations}}
		,
	author={{
			MCoppola
		} and {
			SCuraba
		} and {
			MGrammatikakis
		} and {
			RLocatelli
		} and {
			GMaruccia
		} and {
			FPapariello
		} and {
			LPieralisi
		}}
		
		
		
		
		
		
	
	
		,
	journal={{International Journal of Soft Computing and Engineering (IJSCE)}}
		2231-2307
		
			1
			,
	year={January 2012}
		
	

}

@incollection{b12,
	
	
		,
	title={{Network on Chip for 3D Mesh Structure with Enhanced Security Algorithm in HDL Environment}}
		,
	author={{
			AdeshKumar
		} and {
			SonalSinghal
		} and {
			PiyushKuchhal
		}}
		
		
	
	
		,
	journal={{International Journal of Computer Applications}}
		
			59
			17
			
			,
	publisher={IJCA}
		
	

}

@incollection{b13,
	
	
		,
	title={{Performance evaluation and design trade-offs for network-on-chip interconnect architectures}}
		,
	author={{
			PPratim Pande
		} and {
			CGrecu
		} and {
			MJones
		} and {
			AIvanov
		} and {
			RSaleh
		}}
		
		
		
		
	
	
		,
	journal={{IEEE Transactions on Computers}}
		
			54
			8
			
			,
	year={2005}
		
	

}

@incollection{b14,
	
	
		,
	title={{A Network on Chip Simulator}}
	
	
		,
	booktitle={{Sweden Master of Science Thesis in Electronic System Design}}
				
			,
	year={Aug 2002}
			
		
		
			Royal Institute of Technology
		
	
	,
	note={Rikard Thid Thesis on}

}

@incollection{b15,
	
	
		,
	title={{design challenges of technology scaling}}
		,
	author={{
			SBorkar
		}}
	
	
		,
	journal={{IEEE Micro}}
		
			4
			2329
			,
	year={July-August 1999}
		
	

}

@book{b16,
	
	
		,
	title={{Semiconductor Complex Limited, Internet PDF: Data sheets of XC 95 series CPLD}}
		
	

}

@incollection{b17,
	
	
		,
	title={{3D Network-on Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans}}
		,
	author={{
			VitordePaulo
		} and {
			CristinelAbabei
		}}
		
	
	
		,
	journal={{International Journal of Reconfigurable Computing}}
		
			2010
			,
	publisher={Hindawi Publishing Corporation}
		
	
	,
	note={Article ID603059}

}

@incollection{b18,
	
	
		,
	title={{The future of multiprocessor systems-onchips}}
		,
	author={{
			WWolf
		}}
	
	
		,
	booktitle={{Proceedings of the 41 st Design Automation Conference (DAC'04)}}
				the 41 st Design Automation Conference (DAC'04)
		
			,
	year={June 2004}
			
		
	

}

@book{b19,
	
	
		,
	title={{The New Torus Network Design Based On 3-Dimensional Hypercube}}
		,
	author={{
			Hyeong-OkWoo-Seo Ki1
		} and {
			Jae-CheolLee
		} and {
			Oh
		}}
		
		
		
			,
	year={Feb.15-18 2009}
			
		
		
			ICACT
		
	

}

@book{b20,
	
	
		,
	title={{Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network}}
		,
	author={{
			XinWang
		} and {
			JariNurmi
		}}
		
		
			,
	publisher={Hindawi Publishing Corporation VLSI Design Volume2007}
			18372
		
	
	,
	note={14 page}

}